1. Field of the Invention
The present invention relates to a process for incorporating an anti-reflective coating into a CMOS process flow, and in particular, to a process which avoids having to remove a DARC film prior to formation of a silicided contact.
2. Description of the Related Art
Continued reduction in the feature size of integrated circuits requires stringent control over critical dimensions throughout the photolithographic process. Anti-reflective coatings (ARC) are widely used to enhance control over critical dimension by minimizing reflections from the layer sought to be patterned. These anti-reflective coatings include top or bottom organic spin-on materials (BARC) and inorganic dielectric materials (DARC).
BARC materials are organic in composition and are readily selectively etched during resist clean processes that follow the patterning process. However, DARC material is typically inorganic in composition, and must therefore be removed with a different chemistry or remain in place as a dielectric.
When used in patterning a gate structure in a CMOS process flow, DARC is generally required to be removed because its presence interferes with subsequent formation of a low-resistance silicided contact with the polysilicon gate. Unfortunately however, removal of DARC material is difficult and introduces a number of problems. These problems are illustrated in FIGS. 1A-1G, FIGS. 2A-2E, and FIGS. 3A-3E below.
FIGS. 1A-1G show a cross-sectional view of the process steps of a first conventional process flow for forming a CMOS device. FIG. 1A shows the starting point for the process, wherein thin gate oxide 100 is formed over single crystal silicon 102. Polysilicon layer 104 is then formed over gate oxide 100, and etch stop oxide layer 106 is then deposited or grown over the polysilicon layer 104. DARC 108 (typically Si.sub.3 N.sub.4 or SiON) is then formed over etch stop oxide layer 106. Photoresist 110 is then spun. The presence of an additional footer oxide layer 112 beneath photoresist 110 may be necessary to promote adhesion of photoresist 110 to the underlying DARC 108.
Photoresist 110 is patterned during exposure and develop steps. The thickness of layers 108, 110, 106, and 112 are tailored to minimize reflections from polysilicon layer 104 at the wavelength of light utilized during this exposure step.
FIG. 1B shows the next step in the conventional process, wherein using photoresist 110 as a mask, the pattern of the photoresist is transferred to polysilicon layer 104 by etching footer oxide 112, DARC 108, etch stop oxide 106, polysilicon layer 104, and gate oxide 100 in unmasked regions. Photoresist 110 is then stripped.
FIG. 1C shows formation of seal oxide layer 114 by exposing the resulting surface to heat (between around 700-1000.degree. C.) in the presence of an oxidizing ambient. As a result of this oxidation, seal oxide 114a grows over exposed single crystal silicon regions 102 and sidewalls 104a of polysilicon 104. Seal oxide 114b having approximately half the thickness of seal oxide 114a forms over DARC 108. Exposing DARC 108 to heating during this step serves to densify the DARC, enriching it in silicon.
FIG. 1D shows the next step in the conventional process flow, wherein seal oxide layer 114 is exposed to wet etchant (typically dilute HF). This step removes all of seal oxide 114b formed over DARC 108, and approximately one-half of seal oxide 114a formed over silicon regions 102 and 104.
FIG. 1E shows removal of the now-exposed DARC layer 108 by exposure to wet etchant such as hot phosphoric acid, or to dry etchant having a high selectivity relative to etch stop oxide layer 106. Unless the seal oxide layer 114 is of sufficient thickness (&gt;4 nm), overetching can occur during this step, damaging the surface of the single crystal silicon 102 that will later form source and drain regions.
FIG. 1F shows the subsequent implantation of dopant of a first conductivity type into single crystal silicon regions 102, masked by polysilicon 104. This forms lightly-doped drain (LDD) regions 124 aligned to polysilicon 104.
Following an optional thermal diffusion of LDD regions 124 underneath polysilicon gate 104, FIG. 1G shows completion of fabrication of the MOS device by formation of gate spacers 116 along polysilicon sidewalls 104a, implantation of dopant of the first conductivity type to form source/drain regions 118, and removal of etch stop layer 106 and seal oxide 114a. Silicided contacts 120 are then formed on polysilicon gate 104 and source/drain regions 118.
While the process depicted above in FIGS. 1A-1G is sufficient to form a MOS transistor device, this process flow suffers from an important disadvantage. Specifically, unless seal oxide 114 is formed having a thickness adequate to block etchant employed in removing DARC 108, insufficient etch selectivity can result in degradation of the precursor MOS structure during DARC removal. Specifically, overetching during the step shown in FIG. 1E can damage fragile single crystal silicon regions that will later form the source and drain. This is a serious problem if the prescribed feature size requires formation of a seal oxide having a thickness of less than 4 nm.
FIGS. 2A-2E show an alternative conventional process for forming a MOS transistor, in which the DARC is removed during the gate spacer etchback process. The process steps leading up to FIG. 2A are the same as FIGS. 1A-1D shown above.
FIG. 2A shows that rather than etching DARC 108 immediately following removal of overlying thin seal oxide layer 114b, the alternative conventional process performs ion-implantation of dopant of the first conductivity type through remaining seal oxide 114a to form LDD regions 124 aligned to polysilicon gate 104 and the vertical edges of seal oxide 114.
Following an optional thermal diffusion of LDD regions underneath polysilicon gate 104, FIG. 2B shows formation of a spacer dielectric layer 126 over seal oxide 114a, and the polysilicon gate including DARC 108. Spacer dielectric layer 126 may be formed from silicon nitride, or a stack composed of silicon nitride on silicon oxide. Spacer dielectric layer 126 conforms to polysilicon gate 104, becoming vertical along gate sidewalls 104a.
FIG. 2C shows anisotropic etching of conformal spacer dielectric layer 126 to produce sidewall spacers 116 along sidewalls 104a of gate structure 104. DARC 108 previously densified during the seal oxidation step is also removed during this step by the same etchant used to remove the spacer material.
FIG. 2D shows the formation of source/drain regions 118 through implantation of dopant of the first conductivity type and annealing. Subsequent removal of etch stop layer 106 and seal oxide layer 114a exposes surfaces of gate 104 and source/drain 118 prior to formation of silicide contacts. FIG. 2E shows completion of fabrication of the MOS device by formation of silicided contacts 120 to gate 104 and to source/drain regions 118.
Again, while the conventional process depicted above in FIGS. 2A-2E is sufficient to form a MOS transistor device, this process flow also suffers from important disadvantages. Specifically, insufficient etch selectivity of DARC 108 and spacer nitride layer 126 relative to etch stop layer 106 and seal oxide layer 114a shown in FIG. 2C may result in overetching and damage to precursor source/drain single crystal silicon regions.
Moreover, removal of the DARC layer during spacer etchback is not compatible with formation of spacers consisting of a stack of dielectric layers, such as the oxide/nitride spacers commonly employed to form MOS transistors. This is because the oxide layer of the spacer stack will act as an etch barrier during etchback of the nitride spacer layer, leaving the underlying DARC layer intact.
FIGS. 3A-3E show yet another alternative conventional process for forming a MOS transistor. The process steps leading up to FIG. 2A are the same as FIGS. 1A-1D shown above.
FIG. 3A shows ion-implantation of dopant of a first conductivity type through seal oxide 114 to form LDD regions 124 aligned to polysilicon gate 104 and the vertical edges of seal oxide 114.
FIG. 3B shows formation of a spacer dielectric layer 126 over seal oxide 114. Rather than being formed from silicon nitride or a silicon nitride/oxide stack as shown in prior FIG. 2B, spacer dielectric layer 126 is formed from silicon oxide. Spacer dielectric layer 126 conforms to polysilicon gate 104, becoming vertical along gate sidewalls 104a.
FIG. 3C shows anisotropic etching of conformal spacer dielectric layer 126 to produce sidewall spacers 116 along sidewalls 104a of gate structure 104. During this step, varying amounts of seal oxide 114 overlying single crystal regions 102 may also be etched. Unlike in FIG. 2C above, DARC 108 remains substantially unaffected by this etching step.
FIG. 3D shows specific etching of DARC 108 to stop on underlying oxide etch stop layer 106. Employing an etch having insufficient selectivity relative to oxide can also result in the removal of seal oxide layer 114a, exposing single crystal silicon regions 102 to damage during this step. This problem is exacerbated by prior uneven removal of the seal oxide 114 which serves as an etch stop during this step, due to overetching of the spacer oxide layer 126 during the previous step.
FIG. 3E shows completion of fabrication of the MOS device by implantation of dopant of the first conductivity type to form source/drain regions 118, removal of any remaining seal oxide 114a, and formation of silicided contacts 120 to gate 104 and source/drain regions 118.
Again, while the process depicted above in FIGS. 3A-3E is sufficient to form a MOS transistor device, this process flow can also damage the device. Specifically, insufficient etch selectivity during the step shown in FIG. 3D may result in overetching and damage to precursor single crystal silicon source/drain regions. This is partly due to the fact that the spacer etchback step shown in FIG. 3C may actually leave oxide of varying thicknesses over the device.
Given the difficulties of conventional process flows requiring removal of DARC material during formation of silicided contacts, there is a need in the art for a CMOS process which avoids removal of the DARC coating over polysilicon prior to formation of silicided contacts.